module rst_delay(
	input clk50m			,
	input i_rst_n			,
	output reg o_rst_n	
);
	
	reg [20:0] cnt;
	
	always @ (posedge clk50m or negedge i_rst_n)
	if (!i_rst_n)
		begin
			cnt <= 0;
			o_rst_n <= 0;
		end
	else if (cnt[20])
		begin
			o_rst_n <= 1;
		end
	else 
		begin
			cnt <= cnt + 1'b1;
			o_rst_n <= 0;
		end


endmodule 